As technology continues to scale, devices with conventional source/drain contacts will experience severe problems with respect to shorting from gate to source/drain (e.g., due to a decrease in gate-to-gate pitch). As such, borderless source/drain contacts (or self-aligned source/drain contacts) are currently being utilized to overcome such issues. To realize borderless contacts in an RMG integration scheme, a dielectric capping layer is formed on the gate to isolate the gate from the source/drain contact. For example, FIGS. 1A through 1E schematically illustrate one approach for forming a capping layer to enable borderless contacts (or self-aligned contacts). As shown, in FIG. 1A, a device may include gate structure 101, high-k dielectric layer 103, nitride spacers 105 on opposite sides of gate structure 101, source/drain regions 107, oxide 109 adjacent nitride spacers 105, and substrate 111 below gate structure 101. In addition, gate structure 101 may include metal gate structure 113 (e.g., made of aluminum (Al), tungsten (W), etc.) and metal liner 115 (e.g., made of work-function metals). As depicted, in FIGS. 1B and 1C, the metal gate structure 113 may be recessed, followed by a recess of metal liner 115. Then, in FIGS. 1D and 1E, nitride 117 is deposited and polished to form gate cap 119 over gate structure 101.
However, the process described in FIGS. 1B and 1C is an unlanded etch process that can usually only be achieved with a fixed time etch. It is naturally very difficult to control the metal recess process without an etch stop layer. In this case, controlling the etch depth is extremely difficult since any tool fluctuation during the fixed time etch could result in a change in etch depth. Moreover, it is even more difficult to uniformly recess gate structures with complicated metal liners. Various devices (e.g., NFET, PFET, etc.) on the same wafer may include different work-function metal liners for their gate structures, the metal liners may be of varying thickness, and metal liner material may frequently be modified based on the implemented technology. For example, FIGS. 2A through 2D schematically illustrate an example of uneven depths of metal gate structures and metal liners resulting from a typical recess of gates with varying metal compositions. By way of example, the structure in FIG. 2A may be an NMOS device, and the structure in FIG. 2B may be a PMOS device. Each device may, for instance, include gate structure 201, high-k dielectric layer 203, nitride spacers 205, source/drain regions 207, and oxide 209. As shown, the gate structure 201a of the NMOS device may include metal gate structure 213 along with metal liner 215, and the gate structure 201b of the PMOS device may include metal gate structure 217 along with metal liners 219 and 221. As shown, in FIGS. 2C and 2D, the depths of upper surfaces of the gate structures 201 of the NMOS and the PMOS device may be different after a typical recess (e.g., as depicted by indicator 225). However, to enable efficiency in the manufacturing process, recess of such complex metal compositions should be uniform across the wafer, from wafer-to-wafer, from lot-to-lot, etc.
A need therefore exists for methodology enabling recessing and capping of gate structures with varying metal compositions, along with devices formed by such methods.